发明名称 VOLTAGE GENERATING CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a voltage generating circuit enabling to reject semiconductor memory devices each having potential failure in a shipment test by detecting a decrease in level of a step-up voltage due to unsteady leak current and broadcasting a test result to the outside, and to provide a method for testing a semiconductor device having the voltage generating circuit. <P>SOLUTION: A charge pump circuit 200 is provided with a pump circuit 110, a level detecting circuit 111, an oscillator circuit 112, a level decrease detecting circuit 130 and a detection result holding circuit 131. The level decrease detecting circuit 130 is provided with a voltage division circuit DV2 for dividing a reference voltage VREF1 used in the level detecting circuit 111 and outputting a reference voltage VREF2 having a level lower than that of the reference voltage VREF1; and a comparator CP2 for inputting a divided voltage VDIV of a step-up voltage VP generated in the level detecting circuit 111 and the reference voltage VREF2. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2009232486(A) 申请公布日期 2009.10.08
申请号 JP20080070879 申请日期 2008.03.19
申请人 RENESAS TECHNOLOGY CORP 发明人 SUZUKI TAKANOBU;TANIDA SUSUMU
分类号 H02M3/07;G11C16/02;G11C16/06;G11C29/04 主分类号 H02M3/07
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