METHOD AND DEVICE FOR IMPROVING STABILITY OF 6T SGT CMOS SRAM CELL

摘要

A device structure of a 6T SGT CMOS SRAM cell having a sufficiently high SNM and its manufacturing method. An SGT device comprises an access NMOS device using a sidewall surface as a first crystal plane to provide a first carrier mobility, a pulldown NMOS device using a sidewall surface as a second crystal plane to provide a second carrier mobility, and a pullup PMOS device using a sidewall surface as a third crystal plane to provide a third carrier mobility, and at least one of the first, second, and third crystal planes differs from the other two crystal planes. This constitution is formed from SGT transistors having a relatively low gain and a low carrier mobility plane and SGT transistors having a relatively high gain and a high carrier mobility plane. The SGT having the high-mobility plane has a higher gain than the SGT having the low-mobility plane.