EFFICIENT, PROGRAMMABLE AND SCALABLE LOW DENSITY PARITY CHECK DECODER

摘要

An LOPC decoder suitable (or a range of codeblock sizes and bit-rates, which is also suitable for both ASIC and FPGA implementations, are provided The LOPC decoder can be optimized for either elRA based H matrices or for general H matrices, as may be desirable An H parity matrix can be constructed and/or manipulated to arrange the bit-node message "columns" to facilitate mapping to MPB "columns" and corresponding access via LUT pointer tables to minimize processing cycles.