| 摘要 |
Power wiring comprises a first-layer power wiring cluster in which VDD wiring trace and VSS wiring trace of different potentials at single trace width are arranged alternatingly; a second-layer power wiring cluster, disposed in a layer overlying the first-layer power wiring cluster, in which a VDD wiring trace and a VSS wiring trace of different potentials at single trace width are arranged alternatingly; and vias, placed in areas where the first-layer power wiring cluster and second-layer power wiring clusters intersect three-dimensionally, for electrically connecting wiring traces of the same potential in the first-layer power wiring cluster and wiring traces of the same potential in the second-layer power wiring cluster. A signal-wiring formation area is provided between mutually adjacent first-layer power wiring clusters and between mutually adjacent second-layer power wiring clusters. Design rule violation regarding via density is avoided without decline in integration or an increase in chip area. |
