| 摘要 |
In a switched-capacitor circuit such as a DAC, charges are accumulated by a plurality of sampling capacitors in dependence upon input digital data during a sampling phase; then, during a sharing phase these charges are shared with a holding capacitor which is connected across an opamp. In the so-called bipolar charging type switched-capacitor DAC, the signal provided by the sampling capacitors is doubled by connecting their opposite sides to positive and negative reference voltages during the sampling phase. However, parasitic capacitances associated with the sampling capacitors then cause a disturbance to the input of the operational amplifier during the sharing phase. By equalising the input sides of the sampling capacitors to a reference voltage, prior to the sharing phase, this disturbance is avoided thereby allowing a low-power opamp to be employed in the DAC. This equalising can be achieved by adding a short equalising clock phase between the usual sampling and sharing clock phases of the DAC.
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