PHASE LOCK LOOP CIRCUIT

摘要

A Phase Locked Loop (PLL) circuit (2) comprises a phase detector arrangement (8, 10) having a first input for receiving a reference signal, a second input and an output (13) for providing a control signal, and a voltage controlled oscillator (VCO) arrangement (3). The VCO arrangement (3) includes a VCO (4) having a first input (5) for receiving the control signal, a second input (11 ) and an output (7) for providing an output signal having a frequency dependent on the control signal. The output of the VCO (4) is coupled to the second input of the phase detector arrangement (8, 10) via a feedback path. The VCO arrangement (3) further includes a control circuit (6) for receiving the control signal and being coupled to the second input (11 ) of the VCO (4). The control circuit (6) is arranged in operation to provide an adjustment signal to the VCO (4) selectively and in dependence on a level of the control signal such that the level of the control signal is adjusted to maintain the control signal within a predetermined operating range.