发明名称 |
MACRO VERIFICATION METHOD |
摘要 |
<P>PROBLEM TO BE SOLVED: To allow early detection of an operative failure in a macro of a master block and a slave block in a system LSI in a bus connection state. <P>SOLUTION: A test circuit is embedded in the macro of the master block and the slave block in the system LSI in which a plurality of function blocks are connected through the bus, and conducts a macro control operation for controlling the macro and a macro verification operation for determining a normality/abnormality of a macro operation. A verification environment is built, and connects the bus and the macro in which the test circuit is embedded. A bus connection verification and a function verification are conducted in the macro of the master block and the slave block. <P>COPYRIGHT: (C)2010,JPO&INPIT |
申请公布号 |
JP2009222500(A) |
申请公布日期 |
2009.10.01 |
申请号 |
JP20080066044 |
申请日期 |
2008.03.14 |
申请人 |
FUJITSU MICROELECTRONICS LTD |
发明人 |
NISHIMURA TAKEHIKO;MATSUMOTO TAKAHIRO;OGAWA YOSHIMASA |
分类号 |
G01R31/28;G06F11/22;H01L21/822;H01L27/04 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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