| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a simplified configuration and including a data transfer circuit capable of reducing latency. SOLUTION: The semiconductor storage device includes a read clock generation control circuit 110, first to fourth amplification circuits 101<SB>1</SB>to 101<SB>4</SB>which amplify data read from first to fourth addresses, based on the clock, a first multiplexer (hereinafter referred to as MUX) 102<SB>1</SB>which selects and outputs first and second input data corresponding to even-numbered addresses, a second MUX 102<SB>2</SB>which selects and outputs third and fourth input data corresponding to odd-numbered addresses, latch circuits 103<SB>1</SB>and 103<SB>2</SB>for second and fourth output data, a third MUX 105<SB>1</SB>which outputs the first and third input data in an order in which the data has been read, a fourth MUX 105<SB>2</SB>which outputs second and fourth input data in an order in which the data has been read, first and second registers which receive outputs of the third and fourth MUXs, and a fifth MUX 108 which outputs a total of four outputs of the first and second registers in synchronization with both edges of a clock signal. COPYRIGHT: (C)2010,JPO&INPIT |
