发明名称 |
Method for Training Dynamic Random Access Memory (DRAM) Controller Timing Delays |
摘要 |
Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller (114, 116) are trained. A left edge of passing receive enable delay values is determined (530). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (540). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (550); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set (560).
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申请公布号 |
US2009244997(A1) |
申请公布日期 |
2009.10.01 |
申请号 |
US20080059653 |
申请日期 |
2008.03.31 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
SEARLES SHAWN;ASKAR TAHSIN;HAMILTON THOMAS H.;HOUSTY OSWIN |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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