| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a COL semiconductor package to avoid electrical short caused by wire bonding and to facilitate the layouts of the leads at a lower surface of a chip with smaller die pads or without die pad. <P>SOLUTION: The COL semiconductor package primarily includes: a plurality of leadframe's leads 210; a chip 220; a plurality of bonding wires 230; an insulation tape 240; and an encapsulant 250. Each lead has a plurality of carrying bars 211, a plurality of bonding finger 212, and a plurality of connecting lines 213 for connecting the carrying bar with the bonding finger. The chip has a main surface 221 and a back surface 222, wherein a plurality of bonding pads 223 are disposed on the main surface and the back surface is attached to the carrying bars 210. The bonding pads 223 are connected to the bonding fingers 212 by the bonding wires 230, wherein at least one of the plurality of bonding wires 230 overpasses one of the connecting lines 213A without electrical connection. The insulation tape 240 is attached to the connecting lines 213. The encapsulant 250 encapsulates the chip 220, the bonding wires 230, the insulation tape 240, the bonding fingers 212, and the connecting lines 213. <P>COPYRIGHT: (C)2010,JPO&INPIT |
