| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve a data processing system which avoids the competition of asynchronous access to a storage part without using the clock signal of an arithmetic control part, and surely read decided data. Ž<P>SOLUTION: This invention relates to the data processing system for asynchronously writing data from a plurality of arithmetic control parts in a shared storage part, wherein the system includes: a clock generation circuit for generating a clock signal as an operation reference installed separately from the clock of the arithmetic control part, and for generating a selection signal to select write-in; a bus switching circuit for selecting data to be input from the plurality of arithmetic control parts according to the selection signal; and a signal generation circuit for generating a write-in signal synchronously with the clock signal so that the data can be written in the storage part by time-division according to the selection signal. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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