| 摘要 |
A receiving unit 20 receiving a description expressing a finite state machine comprising states 0, 1, 2, . . . , N-1; a dividing unit 30 dividing the states 0, 1, 2, . . . , N-1 into groups 0, 1, 2, . . . , M-1, wherein the dividing unit allocates the states 0, 1, . . . , L[0]-1 to the group 0, allocates the states L[0], L[0]+1, . . . , L[1]-1 to the group 1, allocates the states L[1], L[1]+1, . . . , L[2]-1 to the group 2, . . . , and allocates the states L[M-2], L[M-2]+1, . . . , L[M-1]-1=N-1 to the group M-1, and a generating unit 40 generating a register transfer level description so that decoders which acquire the current state are generated for each group are provided.
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