| 摘要 |
PROBLEM TO BE SOLVED: To provide a technique for reducing useless data transfer between storage hierarchical units while maintaining a cache coherence in a cache memory system applied to a data processing apparatus using a plurality of processors. SOLUTION: In the cache memory system, each of a plurality of processors is can execute a no-data transfer store command, and each of a plurality of first storage hierarchical units outputs a transfer-control signal in response to occurrence of a cache miss hit when executing the no-data transfer store command by the corresponding processor. A control unit updates, when the transfer control signal is output from the first storage hierarchical unit of a first processor contained in the plurality of processors, state information of the first storage hierarchical unit of the first processor without performing data transfer from at least a second storage hierarchical unit to the first hierarchical unit of the first processor with respect to a storage area designated by the first storage hierarchical unit of the first processor. COPYRIGHT: (C)2010,JPO&INPIT |
