| 摘要 |
In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. A method in a computer-aided design system for generating a functional design model of a fractional-N phased-lock-loop (PLL) structure is provided in one embodiment. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit is presented in another embodiment.
|
