| 摘要 |
<p>A cache memory which allows shortening of a period required for communication processing when computing and communicating are performed independently. The cache memory (103) comprises a data storage means (103a) which is provided with a plurality of words into which data from a CPU (101) can be written, an address storage means (103b) which stores addresses individually associated with the respective words from among a plurality of addresses, and a control means (103c) which when a read instruction and an optional address are received out of a communication device (102) and the address is contained in the address storage means (103b) in the situation, reads data from a word associated with the address and provides the data to the communication device (102) but when the address is not contained in the address storage means (103b), reads data associated with the address out of a memory (104), provides the data to the communication device (102), and does not write the data into the data storage means (103a).</p> |
