Semiconductor memory device having sense amplifier operable as a semi-latch type and a full-latch type based on timing and data sensing method thereof

摘要

A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, a row decoder selecting one of the rows and activating the selected row, a bit-line sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns, a data-bus sense amplifier detecting and amplifying data output from the bit-line sense amplifier, and a control logic block enabling the bit-line and data-bus sense amplifiers in a reading operation, operating the data-bus sense amplifier in a semi-latch type mode for a predetermined period, and operating the data-bus sense amplifier in a full-latch type mode after the predetermined period.