发明名称 Method of gain error calibration in a pipelined analog-to-digital converter or a cyclic analog-to-digital converter
摘要 The invention provides a method of gain error calibration in a pipelined analog-to-digital converter (ADC). In one embodiment, a first stage and a second stage of the pipelined ADC share a common operational amplifier. The first stage is requested to generate the stage output signal thereof according to a first correction number. The second stage is also requested to generate the stage output signal thereof according to a second correction number. A plurality of stage output values generated by stages of the pipelined ADC are collected. The stage output values are respectively correlated with the first correction number and the second correction number to estimate a first gain error estimate of the first stage and a second gain error estimate of the second stage. The first gain error estimate and the second gain error estimate are weighted to obtain a predicted gain error for gain error calibration in the first stage and the second stage.
申请公布号 US7595748(B2) 申请公布日期 2009.09.29
申请号 US20080117833 申请日期 2008.05.09
申请人 MEDIATEK INC. 发明人 TU YU-HSUAN
分类号 H03M1/06 主分类号 H03M1/06
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