发明名称 DRAM APPARATUS
摘要 PROBLEM TO BE SOLVED: To reduce a peak current when switching a word line to a non-selection state from a selection state, and reduce the resultant noise. SOLUTION: A DRAM apparatus has a bit line, a word line and a memory cell, and further has a word line potential control circuit that connects the word line and a counter electrode HVC1P of a plate of the memory cell during a predetermined period when a potential of the word line WL is switched from a selection potential VBOOT to a non-selection potential VNB. By this means, it is possible to reduce noise. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009217896(A) 申请公布日期 2009.09.24
申请号 JP20080060833 申请日期 2008.03.11
申请人 NEC ELECTRONICS CORP 发明人 TAKAHASHI HIDEKI
分类号 G11C11/407 主分类号 G11C11/407
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