| 摘要 |
<P>PROBLEM TO BE SOLVED: To supply a stable reproduction clock, regardless of a jitter component contained in a reception burst data signal by shortening the time for bit synchronization with the reception burst data signal. <P>SOLUTION: The clock data recovery circuit includes: an interpolator section 46 for generating a reference clock having the same frequency as that of a reception burst data signal and two kinds of determination clocks having phases different from that of the reference clock; and phase adjustment control section 45 capable of changing the phase of the reference clock for the unit of M/2π. In the first phase adjustment timing after burst data signal reception start, a phase change amount is enlarged and in the second timing and thereafter, the change amount is made smaller than the previous phase change amount, so that a reproduction clock is generated while fast bit-synchronizing with the reception burst data signal. <P>COPYRIGHT: (C)2009,JPO&INPIT |
