发明名称 POWER SUPPLY NOISE ANALYSIS METHOD, APPARATUS AND PROGRAM FOR ELECTRONIC CIRCUIT BOARD
摘要 PROBLEM TO BE SOLVED: To provide a method and device for reproducing the mechanism of the generation of a power source noise, and for grasping the power source noise in the design stage of a printed circuit board, and for calculating input impedance between the power source/GND of an LSI. SOLUTION: The power source input impedance of an LSI is calculated from the number of output buffers of an LSI, the output impedance of the output buffer, LSI terminal, package, the characteristic impedance of the power source/GND of a chip terminal section, the characteristic impedance of a signal, the characteristic impedance of wiring connected to the LSI output terminal, and the damping resistance of an output signal. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009217622(A) 申请公布日期 2009.09.24
申请号 JP20080061590 申请日期 2008.03.11
申请人 NEC CORP 发明人 KASHIWAKURA KAZUHIRO
分类号 G06F17/50;G01R29/26;H05K3/00 主分类号 G06F17/50
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