SCALABLE ELECTRICALLY ERASEABLE AND PROGRAMMABLE MEMORY
摘要
<p>A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.</p>
申请公布号
WO2009117219(A1)
申请公布日期
2009.09.24
申请号
WO2009US34973
申请日期
2009.02.24
申请人
CATALYST SEMICONDUCTOR, INC.;GEORGESCU, SORIN S.;COSMIN, A. PETER;SMARANDOIU, GEORGE
发明人
GEORGESCU, SORIN S.;COSMIN, A. PETER;SMARANDOIU, GEORGE