发明名称 METHOD AND SYSTEM FOR VALIDATING A PROCESSOR IN A SEMICONDUCTOR ASSEMBLY
摘要 A method of conducting validation is provided. The method includes providing a processor that does not include a validation function and providing an auxiliary die coupled to the processor. The method also includes receiving validation data from the processor in the auxiliary die and conducting validation of the processor in the auxiliary die.
申请公布号 US2009240454(A1) 申请公布日期 2009.09.24
申请号 US20080054277 申请日期 2008.03.24
申请人 PATRA PRIYADARSAN 发明人 PATRA PRIYADARSAN
分类号 G06F19/00 主分类号 G06F19/00
代理机构 代理人
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