| 摘要 |
A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.
|
