| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory system for more shortening a time required since a reset request is received until it is actually shifted to reset processing than a conventional manner. <P>SOLUTION: This memory system is provided with a DRAM 20 having a WC 21: an FS 12 which performs readout/write-in by page unit, and performs deletion by block unit; an MS 11 which performs readout/write-in by track unit, and performs deletion by block unit; an FSIB 12a being the input buffer of the FS 12; an MSIB 11a being the input buffer of the MS; and a controller which performs the storage processing of data. The MSIB 11a is provided with an FSBB 12ac which stores the data written in the WC 21, and the controller saves the data written in the WC 21 to the FSBB 12ac when receiving a reset request from a host device. <P>COPYRIGHT: (C)2009,JPO&INPIT |
