发明名称 |
SAMPLE-HOLD CIRCUIT, INTEGRATED CIRCUIT DEVICE, ELECTRO-OPTIC DEVICE, AND ELECTRONIC EQUIPMENT |
摘要 |
PROBLEM TO BE SOLVED: To provide a sample-hold circuit, an integrated circuit, an electro-optic device, and electronic equipment capable of achieving a proper sample hold operation while suppressing the circuit scale. SOLUTION: The sample-hold circuit includes: an operational amplifier; a sampling capacitor provided between an input node of the sample-hold circuit and a summing node that is a node of a first input terminal of the operational amplifier; and a feedback switch element provided between an output terminal and the summing node of the operation amplifier and constructed with a transfer gate. The feedback switch element includes a feedback P type transistor TFP and a feedback N type transistor TFN whose drain is connected to a summing node line LNEG. A shield pattern SLA1 is formed in a region between drain contacts CDP, CDN of a feedback P type transistor TFP and a feedback N type transistor TFN and source contacts CSP and CSN. COPYRIGHT: (C)2009,JPO&INPIT
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申请公布号 |
JP2009212457(A) |
申请公布日期 |
2009.09.17 |
申请号 |
JP20080056516 |
申请日期 |
2008.03.06 |
申请人 |
SEIKO EPSON CORP |
发明人 |
SHIN CHIHIRO;KIYA HIROSHI;KAMIJO HARUO;NISHIMURA MOTOAKI;MAKI KATSUHIKO;ITO SATORU |
分类号 |
H01L21/822;G11C27/02;H01L27/04 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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