发明名称 GATE OXIDE PROTECTED I/O CIRCUIT
摘要 An integrated circuit comprises a first input node and a second input node, an output node; a first output transistor of a first type and a second output transistor of a second type, and a first clamping transistor of the second type and a second clamping transistor of a second type. The first clamping transistor, the first output transistor, the second clamping transistor, and the second output transistor are coupled in series across a first power supply terminal and a second power supply terminal. The first input node is coupled to a gate of the first output transistor. The second input node is coupled to a gate of the second output transistor. The output node is coupled to a common node of the first output transistor and the second clamping transistor. A gate of the first clamping transistor is coupled to a first reference voltage. A gate of the second clamping transistor is coupled to a second reference voltage.
申请公布号 US2009231016(A1) 申请公布日期 2009.09.17
申请号 US20090471267 申请日期 2009.05.22
申请人 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. 发明人 WANG DAR-WOEI;LIU YI-HENG
分类号 H03L5/00 主分类号 H03L5/00
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