| 摘要 |
A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual Phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
|
