发明名称 |
COMPUTER PROGRAM INSTRUCTION ARCHITECTURE, SYSTEM AND PROCESS USING PARTIAL ORDERING FOR ADAPTIVE RESPONSE TO MEMORY LATENCIES |
摘要 |
The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.
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申请公布号 |
US2009235035(A1) |
申请公布日期 |
2009.09.17 |
申请号 |
US20090404957 |
申请日期 |
2009.03.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BACON DAVID F.;SHEN XIAOWEI |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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