发明名称 BIT REDUCTION DEVICE
摘要 <p>A bit reduction apparatus preventing visual recognition of beat noise while maintaining gradation is presented. The bit reduction apparatus of the invention changes over the bit reduction operation by executing simple discarding process and noise shaping process, on the basis of at least any one of input signal state, user's setting state, and apparatus setting state. <IMAGE></p>
申请公布号 EP1460834(A4) 申请公布日期 2009.09.16
申请号 EP20030792662 申请日期 2003.08.08
申请人 PANASONIC CORPORATION 发明人 HATANO, TAKAHISA
分类号 H04N1/405;H04N1/41;H04N5/06;H04N5/202;H04N5/21;H04N5/57;H04N5/66;(IPC1-7):H04N5/21 主分类号 H04N1/405
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