发明名称 |
PROCESS FOR SEMICONDUCTOR WAFER-LEVEL CHIP SCALE PACKAGES |
摘要 |
<p>In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.</p> |
申请公布号 |
EP1273039(B1) |
申请公布日期 |
2009.09.16 |
申请号 |
EP20010924799 |
申请日期 |
2001.04.06 |
申请人 |
SILICONIX INCORPORATED |
发明人 |
KASEM, MOHAMMED Y.;HO, YUEH-SE;LEE, SHAWN LUO;CHEN, CHANG-SHENG;TJHIA, EDDY;LAN, BOSCO;KOREC, JACEK;BHALLA, ANUP |
分类号 |
H01L21/768;H01L29/41;H01L21/3205;H01L21/336;H01L23/12;H01L23/31;H01L23/48;H01L23/52;H01L29/78 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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