<p>Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device.</p>
申请公布号
WO2009111174(A1)
申请公布日期
2009.09.11
申请号
WO2009US34491
申请日期
2009.02.19
申请人
RAMBUS INC.;HAUKNESS, BRENT, S.;SHAEFFER, IAN;BRONNER, GARY, B.
发明人
HAUKNESS, BRENT, S.;SHAEFFER, IAN;BRONNER, GARY, B.