PROCESSOR COMPRISING A CACHE MEMORY

摘要

A processor processes data (VC) comprising respective segments that refer to respective data portions. A segment is accompanied by an indication of a data portion to which the segment refers. A segment may be, for example, a smaller block of a video macroblock. The processor comprises a cache memory arrangement (CMA) that can operate in a normal mode and in a bypass mode. In the normal mode, a request (RQ) for a data portion is presented to a cache memory (CM). In the bypass mode, such a request is systematically presented to a main memory (MM). A cache mode controller (CMC) analyzes the respective indications (MPS) accompanying a group (MBC) of segments that will be successively processed, so as to establish a degree of disparity in position between the respective data portions which are referred to. The cache memory arrangement (CMA) operates in the bypass mode if the degree of disparity exceeds a predefined limit and in the normal mode otherwise.