| 摘要 |
<p>A wireless communication device incorporates a Radix-4 algorithm-based high-speed Fourier-transform processor having a plurality of butterfly operation means linked in two or more stages via a multiplier, wherein each of the butterfly operation means has a first two-input/two-output butterfly operation unit and a second two-input/two-output butterfly operation unit which are connected in serial as a pair. A Radix-4 algorithm-based high-speed inverse Fourier-transform processor is implemented by inverting codes of a twiddle factor in the multiplier on the high-speed Fourier-transform processor and further by reversing codes converted by a swapping process at a subsequent-stage butterfly operation unit BF2B in a real number component and an imaginary number component.</p> |
