TIME DIGITAL CONVERTER, DIGITAL PLL FREQUENCY SYNTHESIZER, TRANSMITTER-RECEIVER, AND RECEIVER

摘要

A variable delay circuit (101) generates a plurality of delay signals (D(1), D(2), , D(n)). An output holding circuit (102) takes in the delay signals (D(1), D(2), , D(n)) in synchronization with the transition of a reference signal (Sref). A selector (104) supplies an input signal (Sin) to the variable delay circuit (101) in an ordinary mode and supplies one of the delay signals (D(1), D(2), , D(n)) to the variable delay circuit (101) in a calibration mode. A frequency measurement circuit (105) counts the number of times of transition of one of the delay signals (D(1), D(2), , D(n)) within a predetermined frequency measurement period. A delay amount calibration circuit (106) adjusts the delay time of the variable delay circuit (101) so that the number of times of transition counted by the frequency measurement circuit (105) in the calibration mode approaches a target value corresponding to the frequency of the input signal (Sin).