发明名称 MEMORY DEVICE, MEMORY SYSTEM, AND ACCESS TIMING ADJUSTING METHOD IN MEMORY SYSTEM
摘要 <p>A memory device (103) comprises a memory device control unit (140), a delay adjustment storage unit (170) for storing timing adjustment data that is data read by values of both "0" and "1" at the rise and fall of a strobe signal, memory cells (174), and a selector (172) for switching a connection to the delay adjustment storage unit or the memory cells. A memory interface (102) reads timing adjustment data stored in the delay adjustment storage unit (170) while changing timing and searches a readable timing range, from which a read timing is selected and set.</p>
申请公布号 WO2009110040(A1) 申请公布日期 2009.09.11
申请号 WO2008JP02296 申请日期 2008.08.25
申请人 PANASONIC CORPORATION;TAKAI, YUJI 发明人 TAKAI, YUJI
分类号 G06F12/00;G11C11/401 主分类号 G06F12/00
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