| 摘要 |
PROBLEM TO BE SOLVED: To stably perform the serial transmission of an imaging signal at a high speed. SOLUTION: An imaging chip 42 equipped with a solid state imaging element 44 is connected to a processor 11 through signal lines 49a-49e. The imaging signal produced by the solid state imaging element 44 is serially transmitted to the processor 11 through the signal line 49a. The processor 11 is equipped with a clock data recovery (CDR) circuit 79. The CDR circuit 79 extracts a clock signal RCLK from the imaging signal SDT input through the signal line 49a to produce a data signal RSDT synchronizing to the extracted clock signal RCLK in phase. By this constitution, the speedup and stabilization of the transmission of the imaging signal is achieved without generating the problem wherein timing skew occurs between the transmitted data signal and the clock signal. COPYRIGHT: (C)2009,JPO&INPIT
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