发明名称 CIRCUIT VERIFICATION APPARATUS, A METHOD OF CIRCUIT VERIFICATION AND CIRCUIT VERIFICATION PROGRAM
摘要 A circuit verification apparatus for verifying justice of wiring connections of PWB is provided. The circuit verification apparatus includes a net list reduction part for generating a reduction net list in which unnecessary components and connections for verification are eliminated from connection relationships for all components used in the PWB; a connection rule for defining conditions of a pair of start point and end point of each expected connection by using variables and function; a rule expanding part for developing the connection rule by using conditions of a pin specified to the start point, determining end point conditions corresponding to the start point and generating a post-development rule including developed conditions of the start point and end point; and a net list and rule matching verification part for verifying matching state of each connection with referring to the reduction net list and the post-development rule, and outputs a verification result.
申请公布号 US2009228848(A1) 申请公布日期 2009.09.10
申请号 US20090397018 申请日期 2009.03.03
申请人 KUMAZAKI MASAHITO 发明人 KUMAZAKI MASAHITO
分类号 G06F17/50 主分类号 G06F17/50
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