发明名称 PERFORMANCE MONITOR CIRCUIT AND PERFORMANCE MONITOR METHOD
摘要 PROBLEM TO BE SOLVED: To provide a performance monitor circuit capable of specifying a sampling interval by clock cycle and a method thereof. SOLUTION: The performance monitor circuit and the performance monitor method are equipped with a buffer, stored a received packet in the transaction layer of a PCI Express in the buffer, and connected to the PCI express component transmitting the packet stored in the buffer. The performance monitor circuit includes: a first counter for measuring a data volume of the packet sent from the buffer; a second counter for measuring the number of clock cycles in which a packet exists in the buffer; a third counter for measuring the number of clock cycles in which a packet to be transmitted exists in the buffer, but it could not be transmitted; and a control circuit for performing control to repeat the measurement by first to third counters at a predetermined time interval. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009205334(A) 申请公布日期 2009.09.10
申请号 JP20080045730 申请日期 2008.02.27
申请人 HITACHI LTD 发明人 MURAKAMI SHOKI;TOKORO MASAHIRO
分类号 G06F13/38 主分类号 G06F13/38
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