| 摘要 |
A storage unit of a single-conductor non-volatile memory cell is described, which includes an isolation layer in a substrate, a storage transistor and an erasing transistor. The storage transistor includes a first well of a first conductivity type in the substrate beside the isolation layer, a floating gate crossing over the isolation layer and including a first segment over the first well, and two source/drain regions of a second conductivity type in the first well beside the first segment of the floating gate. The erasing transistor includes a second well of the first conductivity type located in the substrate and separated from the first well by the isolation layer, a second segment of the floating gate over the second well, and a well pickup region of the first conductivity type in the second well beside the second segment of the floating gate.
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