| 摘要 |
A method for identifying weak points in the geometry of an integrated circuit, and the critical process condition at which the weak point is likely to fail. The simulation means of the OPC process is used to generate the simulated wafer structure, not only in ideal process conditions, but also at other, non-ideal process conditions. The difference in aerial image intensity of the non-ideal simulations is indicative of the presence and extent of a weak point. The edge-placement error between the ideal simulation and the simulation in which a weak point has been identified is used to determine the location of the weak point in the design. |
