发明名称 Method for forming planarizing copper in a low-k dielectric
摘要 Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal treatment process. Electropolishing is then used to planarize the second and first conductive films, wherein an electrolyte solution selective to remove the first conductive film faster than the second conductive film is used. An interconnect is formed.
申请公布号 US7585760(B2) 申请公布日期 2009.09.08
申请号 US20060473738 申请日期 2006.06.23
申请人 INTEL CORPORATION 发明人 ANDRYUSHCHENKO TATYANA N.;MILLER ANNE E.
分类号 H01L21/4763 主分类号 H01L21/4763
代理机构 代理人
主权项
地址
您可能感兴趣的专利