| 摘要 |
A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.
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