发明名称 Test pattern generation in residue networks
摘要 Generating a near-minimal test pattern set for overlapping residue circuit trees in a residue network includes resolving a residue function of residue circuits through the network and making note of any gate at which the residue function thereof does not produce the assigned vector output for a given assigned set of input vectors. Where such gates cannot be resolved during one set of vector assignments, the test set that is complete up to the offending gate may be saved, and resolution of the residue function may be started from another node in the network. Multiple test sets may be generated, the combined application of which will exhaustively test each gate in the network.
申请公布号 US7587646(B1) 申请公布日期 2009.09.08
申请号 US20080143043 申请日期 2008.06.20
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 SNETHEN THOMAS JAMES;ASHER CAROLYN
分类号 G06F11/00 主分类号 G06F11/00
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