| 摘要 |
A semiconductor memory device is provided to enable a pin strobe signal within a range of data although a condition inside a chip is changed by improving timing of the pin strobe signal enabled in a parallel test mode. A data compression part(540) compresses data read from memory cells in a parallel test mode, and outputs a compressed result. The data compression part includes exclusive NOR gates and an AND gate for compressing and calculating the data. A replica delay part(550) is modeled like the data compression part, delays a pin strobe signal in a normal mode, and generates a pin strobe signal in a parallel test mode. The replica delay part sends the pin strobe signal in the normal mode to a path like a moving path of the data in the data compression part. The replica delay part includes NOR gate and AND gate like the data compression part. |
