发明名称 CHIP-PACKAGE SIMULATION
摘要 A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.
申请公布号 KR20090094247(A) 申请公布日期 2009.09.04
申请号 KR20097010119 申请日期 2007.11.27
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BEATTIE MICHAEL;KRAUTER BYRON LEE;ZHENG HUI
分类号 G06F17/50;G06F17/40 主分类号 G06F17/50
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