| 摘要 |
An asynchronous pseudo SRAM having compatibility with asynchronous SRAMs. A read request or a write request of data is provided at arbitrary timing to the asynchronous pseudo SRAM, the asynchronous pseudo SRAM includes a memory cell array comprising dynamic memory cells; an array control circuit that is activated in response to an access enable signal, the array control circuit reads data from or writes data in the memory cell array in response to address signals, and the array control circuit activates a busy signal during reading or writing of data; an access reception circuit for receiving the read request or the write request to activate an access wait signal and inactivating the access wait signal in response to the access enable signal; and an access activation circuit for activating the access enable signal in response to activation of the access wait signal and inactivation of the busy signal.
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