发明名称 METHOD AND APPARATUS FOR OPTIMIZING ADVANCED ENCRYPTION STANDARD (AES) ENCRYPTION AND DECRYPTION IN PARALLEL MODES OF OPERATION
摘要 A method and an apparatus for optimizing advanced encryption standard encryption and decryption in parallel modes of operation are provided to accomplish reduction of total latency required for performing AES encryption/decryption calculation. A plurality of data blocks to be performed encryption and decryption are stored in a plurality of registers(300). A calculation in round 0 is successively performed about each of the different data blocks of k stored in 128-bit registers of k(302). The AES(Advanced Encryption Standard) round instruction which is identical to the other rounds is dispatched(304). If there is the other round to the AES calculation, the processing step moves forward the third step(306). If there is no other data blocks processed about the AES calculation, the result of the AES calculation is returned(308,310).
申请公布号 KR20090092735(A) 申请公布日期 2009.09.01
申请号 KR20090017289 申请日期 2009.02.27
申请人 INTEL CORP. 发明人 GUERON SHAY;GRADSTEIN AMIT;SPERBER ZEEV
分类号 G06F9/38;G06F9/06;G06F12/06;G06F12/08 主分类号 G06F9/38
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