INTERLEAVING SYSTEM

摘要

A multi-stage interleaving device comprises: N units of processing parts arranged in tiers. Each processing part comprises an operating memory providing a matrix of storage areas, input terminals receiving bit streams, a data writer writing the bit stream in the storage areas, starting from a top row from left to right. The data writer writes another bit stream to fill unfilled storage areas, starting from a left most column from top to bottom. A data reader is configured to read the bit streams in the matrix, starting from the left mos t column from top to bottom to output a third bit stream in which the bit streams are scattered at intervals. An output terminal is configured to output the third bit stream. A plurality of connections input and output the bit streams with the processing parts. N+1 lines of input connections provide two streams of inpu t bits to the input terminals at the bottom tier. N-1 lines of output connections provide the third stream of bits from the output terminal to one of the inpu t terminals.