| 摘要 |
The frequency of the internal clock is set at ½ of the frequency of an external clock as well as the width of the internal bus is configured to be twice as wide as the width of an external bus. A write control unit controls a bypass unit and a swap circuit unit and, when a plurality of packets are received, writes words of the packets such that headers H of the received packets are respectively arranged alternately in each packet storage sector between an even-numbered queue and an odd-numbered queue. A read control unit reads the words of the packets in parallel by two words at each time from the even-numbered queue and the odd-numbered queue.
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