| 摘要 |
Replaced cell CELL1 is composed of clock buffer circuit CB1 and flip-flop circuit FF1 that latches data at a falling-down time of a clock signal. Clock buffer circuits CB1a-CB1d are cascade-connected to form a clock tree circuit. A scan circuit is composed of scan flip-flop circuits SFF1-SFF4. Replaced cell CELL1 is set in place of the last stage neighboring a scan circuit side between the scan circuit and the clock buffer circuits CB1a-CB1d to easily optimize timing adjustments and layout design.
|
